The present invention relates to technology for packaging semiconductor devices, and more specifically to technology that can be effectively adapted to packages of the surface-mounted type having increased number of pins.
Accompanying the trend toward fabricating computers which have large capacities and which operate at high speeds, attempts have been made to increase the number of pins of packages for mounting logic LSI's and image processing LSI's.
Packages adapted to increasing the number of pins include a pin grid array (hereinafter referred to as PGA) which is of the pin insertion type, as well as PLCC (plastic leaded chip carrier) and QFP (quad flat package) and the like which are of the surface mounting type. Their tendency and technology have been described in, for example, "Denshi Zairyo" published by Kogyo Chosakai Ltd., Sept. 1987, pp. 40-50 and Japanese Patent Laid-Open No. 132465/1988.
Among them, the PGA type enables the whole back surface of the package to be utilized for taking out the lead pins, and is recently drawing attention as a package structure that is best adapted to LSI's that need very many pins such as 300 to 500 pins.